Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, retaining its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory, particularly in the form of memory cards, is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
EEPROM and electrically programmable read-only memory (EPROM) are non-volatile memory that can be erased and have new data written or “programmed” into their memory cells.
A flash EEPROM allows a group of memory cells to be erased together. These devices contain memory cells each having a storage element in the form of a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
The floating gate can hold a range of charge and therefore an EPROM memory cell can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell. An NROM has a similar structure except its storage element is a dielectric layer instead of a floating gate.
Clearly, it is advantageous to have higher numbers of memory states providing greater memory storage density. This requires higher numbers of resolvable threshold voltages. Hence, a power supply must provide precise voltage during programming and reading of the memory cells. Fluctuations in the applied voltage may cause errors in the data being stored if the fluctuations exceed the voltage range for the corresponding memory state.
Also, to improve performance, a large number of memory cells are operated in parallel. This too puts great demands on the power supply. For example, in order to perform a program operation on a row of memory cells whose control gates are connected by the same wordline, the wordline voltage must be raised from a first voltage (e.g. 0V) to a second voltage (e.g. 12–18V) as quickly as possible. The wordline with all the connected control gates may be regarded as a capacitor. Thus, it is equivalent to charging a capacitor from a first voltage to a second voltage.
Program voltage levels used in EPROM memory circuits are higher than the voltages normally used in memory circuits. They are often higher than the voltage supplied to the circuit. These higher voltages are preferably produced within the memory circuit by a charge pump, which in one example essentially dumps charge into the capacitive wordline to charge it to a higher voltage.
FIG. 1. illustrates schematically a charge pump typical of the prior art. The charge pump receives an input at a voltage Vin and provides an output at a higher voltage Vout by boosting the input voltage progressively in a series of voltage multiplier stages. The voltage output is supplied to a load, for example the word line of an EPROM memory circuit. FIG. 1 also shows a feedback signal from the load to the charge pump. The conventional prior art pump turns off in response to a signal indicating that the load has reached a predetermined voltage. Alternatively, a shunt is used to prevent overcharging once the load reaches the predetermined voltage. However, this consumes more power and is undesirable in low power applications.
FIG. 2 illustrates schematically a voltage multiplier stage of the prior art. The stage pumps charge in response to a clock signal shown as “CLK.” When the clock signal is at a low portion of the clock cycle (e.g. 0V) the driver circuit output is LOW. This means that the lower terminal of capacitor C is at 0 volts. An input supplies a voltage Vn-1 through the diode D and provides approximately Vn-1 to the upper terminal of C (ignoring the voltage drop across the diode, D). This will deposit a charge Q on the capacitor, where Q=CVn-1 When the clock signal transitions to a high state the output of the driver circuit is high, for example VCLK and so the lower terminal of C is at VCLK. This will force the upper terminal of C to be (Vn-1+ΔVCLK) since charge, Q, is conserved and C is constant. Thus the output voltage of the voltage multiplier stage is: Vn=Vn-1+ΔVCLK. The driver will drive one side of the capacitor to Vclk, however because of parasitic capacitance the other side will be increased by ΔVCLK, a voltage less than VCLK.
FIG. 3 illustrates the regulated output voltage of a typical charge pump of the prior art while maintaining a voltage Vpp. When the output voltage falls below a margin of Vpp, the pump is turned on. The pump delivers a high current to the load and drives the voltage higher than Vpp. The pump then switches off in response to a feedback signal from the load. The voltage on the load then drops due to leakage current until it reaches a predetermined voltage, lower than Vpp by a fixed amount. Then the charge pump switches on again. This cycle produces the ripples in voltage shown. If these ripples (shown by ΔV) are large they may cause problems by programming a floating gate to the wrong voltage level, or by causing a greater variation in program levels. Previous attempts to regulate the output of charge pump circuits include modifying the clock signal, see U.S. Pat. No. 6,188,590 B1 to Chang et al.
Because voltage ripples may cause errors in EPROM memory circuits, and prior art charge pumps generally give an output with significant ripples, there is a need for a charge pump with ripple reduction capability.